1. Field of the Invention
The present invention relates generally to biasing circuits, and more particularly to an amplified MOS biasing circuit for avoiding latch-up.
2. Discussion of Background Art
Parasitic diodes are typically formed when MOS devices are created within integrated circuits. For instance, in order to create PMOS transistors on a P-doped silicon substrate, N-doped "wells" must first be created within the substrate, then P-doped sources and drains are created within the wells. As is well known in the art, such a series of dopings creates two parasitic P-N diodes. The first diode is between the P-substrate and the N-well. The second diode is between the N-well and the P-source or P-drain. These parasitic transistors are also created when NMOS devices are formed within an N-doped silicon substrate.
When a PMOS transistor and an NMOS transistor are positioned side-by-side within an integrated circuit, a parasitic P-N-P-N Silicon Controlled Rectifier (SCR) circuit is created. As is well known in the art, parasitic SCRs in MOS transistor circuits can cause an undesirable condition called "latch-up." Latch-up occurs when the parasitic SCRs pass so much current that not only can't the integrated circuit's transistors be programmed, but also the integrated circuit could overheat and burn.
Designers typically have approached the latch-up danger either by keeping the parasitic diodes reverse biased or by placing guard-rings around each of the MOS transistors. When the diodes are reverse biased, current does not flow through them and the danger of creating a parasitic SCR is significantly reduced. To keep the parasitic diodes, within the PMOS transistor, reverse biased, the PMOS transistor's N-well must be kept at a higher voltage than the P-substrate, the P-source, and the P-drain. Since many integrated circuits, especially EPROMs, receive a plurality of different voltages, biasing circuits have been created for selecting and applying a maximum voltage to the N-well of the PMOS transistors in that integrated circuit. Note, for NMOS transistors the threat of latch-up is reduced by applying a minimum voltage to a P-well of the NMOS transistors.
These biasing circuits however, typically transition to a high-impedance state when the voltages they are comparing are almost equal. High-impedance results when all of the transistors in a biasing circuit are briefly turned off. Thus, instead of applying a maximum voltage to the N-well of a PMOS transistor, the N-well is allowed to float. When the N-well floats there is a much greater possibility that the PMOS transistor's parasitic diodes will forward bias and the integrated circuit will latch-up.
The other prior art approach toward reducing the danger of latch-up has been to place guard-rings around each of the MOS transistors. The guard-rings serve to isolate each PMOS transistor from its neighboring NMOS transistor and thus discourage parasitic SCRs from forming. However, guard rings consume additional space within an integrated circuit's already very limited area.
What is needed is an apparatus and method for avoiding latch-up in MOS based integrated circuits that addresses the prior art problems described above.